`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2022/01/05 20:44:15
// Design Name: 
// Module Name: axi_uart_ctrl_wrapper
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////

module axi_uart_ctrl_wrapper(
    input           clk,
    input           rst_n,
    input [32-1:0]  s_axi_awaddr,
    input [2:0]     s_axi_awprot,
    output          s_axi_awready,
    input           s_axi_awvalid,
    input [31:0]    s_axi_wdata,
    input [3:0]     s_axi_wstrb,
    input           s_axi_wvalid,            
    output          s_axi_wready,
    output [1:0]    s_axi_bresp,
    output          s_axi_bvalid,  
    input           s_axi_bready,
    input [32-1:0]  s_axi_araddr,
    input [2:0]     s_axi_arprot,
    input           s_axi_arvalid,           
    output          s_axi_arready,
    output [31:0]   s_axi_rdata,
    output [1:0]    s_axi_rresp,
    output          s_axi_rvalid,            
    input           s_axi_rready,            

    input               rxd,
    output              txd
);

Axi4LiteIf    slave(clk);

assign slave.rst_n  = rst_n;

assign slave.awaddr =s_axi_awaddr;
assign slave.awprot =s_axi_awprot;
assign s_axi_awready=slave.awready;
assign slave.awvalid=s_axi_awvalid;
assign slave.wdata  =s_axi_wdata  ;
assign slave.wstrb  =s_axi_wstrb  ;
assign slave.wvalid =s_axi_wvalid ;
assign s_axi_wready = slave.wready;
assign s_axi_bresp  =slave.bresp;
assign s_axi_bvalid =slave.bvalid;
assign slave.bready =s_axi_bready;
assign slave.araddr =s_axi_araddr;
assign slave.arprot =s_axi_arprot;
assign slave.arvalid=s_axi_arvalid;
assign s_axi_arready=slave.arready;
assign s_axi_rdata  =slave.rdata  ;
assign s_axi_rresp  =slave.rresp  ;
assign s_axi_rvalid =slave.rvalid ;
assign slave.rready =s_axi_rready;

axi_uart_ctrl _axi_uart_ctrl(
.rxd     (rxd  ),
.txd     (txd  ),
.slave   (slave)
);



endmodule
